Minimize HardwareSerial Receive and Transmit delays (espressif#3664)

* Minimize HardwareSerial Receive and Transmit delays * Remove uartRxFifoToQueue from esp-hal-uart.h Co-authored-by: Me No Dev <[email protected]>

Author: hreintke

cores/esp32/esp32-hal-uart.c

@@ -208,6 +208,11 @@ uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rx
 uart->dev->conf0.stop_bit_num=ONE_STOP_BITS_CONF;
 uart->dev->rs485_conf.dl1_en=1;
  }
+
+// tx_idle_num : idle interval after tx FIFO is empty(unit: the time it takes to send one bit under current baudrate)
+// Setting it to 0 prevents line idle time/delays when sending messages with small intervals
+uart->dev->idle_conf.tx_idle_num=0; //
+
 UART_MUTEX_UNLOCK();
 
 if(rxPin!=-1){
@@ -265,7 +270,7 @@ uint32_t uartAvailable(uart_t* uart)
 if(uart==NULL||uart->queue==NULL){
 return0;
  }
-returnuxQueueMessagesWaiting(uart->queue);
+return(uxQueueMessagesWaiting(uart->queue)+uart->dev->status.rxfifo_cnt) ;
 }
 
 uint32_tuartAvailableForWrite(uart_t*uart)
@@ -276,12 +281,27 @@ uint32_t uartAvailableForWrite(uart_t* uart)
 return0x7f-uart->dev->status.txfifo_cnt;
 }
 
+voiduartRxFifoToQueue(uart_t*uart)
+{
+uint8_tc;
+UART_MUTEX_LOCK();
+while(uart->dev->status.rxfifo_cnt|| (uart->dev->mem_rx_status.wr_addr!=uart->dev->mem_rx_status.rd_addr)){
+c=uart->dev->fifo.rw_byte;
+xQueueSend(uart->queue, &c, 0);
+ }
+UART_MUTEX_UNLOCK();
+}
+
 uint8_tuartRead(uart_t*uart)
 {
 if(uart==NULL||uart->queue==NULL){
 return0;
  }
 uint8_tc;
+if ((uxQueueMessagesWaiting(uart->queue) ==0) && (uart->dev->status.rxfifo_cnt>0))
+{
+uartRxFifoToQueue(uart);
+ }
 if(xQueueReceive(uart->queue, &c, 0)){
 returnc;
  }
@@ -294,6 +314,10 @@ uint8_t uartPeek(uart_t* uart)
 return0;
  }
 uint8_tc;
+if ((uxQueueMessagesWaiting(uart->queue) ==0) && (uart->dev->status.rxfifo_cnt>0))
+{
+uartRxFifoToQueue(uart);
+ }
 if(xQueuePeek(uart->queue, &c, 0)){
 returnc;
  }