deps: fix zlib compilation for CPUs without SIMD features

Fix the compile flags so that zlib can run on CPUs that do not have SSSE3/SSE4.2/etc. Do not compile zlib with flags that indicate that those features are available, and instead enable them selectively for functions that use them. There are probably better way to do this, e.g. through gyp file modifications as suggested in the issue. However, this patch should do just fine until that happens. Fixes: #32553 PR-URL: #32627 Reviewed-By: Gireesh Punathil <[email protected]> Reviewed-By: Ben Noordhuis <[email protected]> Reviewed-By: Tobias Nießen <[email protected]> Reviewed-By: James M Snell <[email protected]> PR-URL: #45387 Reviewed-By: Rafael Gonzaga <[email protected]>

Author: addaleax

deps/zlib/adler32_simd.c

@@ -50,9 +50,13 @@
 #defineNMAX 5552
 
 #if defined(ADLER32_SIMD_SSSE3)
+#ifndef__GNUC__
+#define__attribute__()
+#endif
 
 #include<tmmintrin.h>
 
+__attribute__((target("ssse3")))
 uint32_tZLIB_INTERNALadler32_simd_( /* SSSE3 */
 uint32_tadler,
 constunsigned char*buf,

deps/zlib/crc32_simd.c

@@ -8,6 +8,9 @@
 #include"crc32_simd.h"
 
 #if defined(CRC32_SIMD_SSE42_PCLMUL)
+#ifndef__GNUC__
+#define__attribute__()
+#endif
 
 /*
  * crc32_sse42_simd_(): compute the crc32 of the buffer, where the buffer
@@ -21,6 +24,7 @@
 #include<smmintrin.h>
 #include<wmmintrin.h>
 
+__attribute__((target("sse4.2,pclmul")))
 uint32_tZLIB_INTERNALcrc32_sse42_simd_( /* SSE4.2+PCLMUL */
 constunsigned char*buf,
 z_size_tlen,

deps/zlib/crc_folding.c

@@ -25,6 +25,10 @@
 #include<immintrin.h>
 #include<wmmintrin.h>
 
+#ifndef__GNUC__
+#define__attribute__()
+#endif
+
 #defineCRC_LOAD(s) \
  do{\
  __m128i xmm_crc0 = _mm_loadu_si128((__m128i *)s->crc0 + 0);\
@@ -41,6 +45,7 @@
  _mm_storeu_si128((__m128i *)s->crc0 + 4, xmm_crc_part);\
  } while (0);
 
+__attribute__((target("sse4.2,pclmul")))
 ZLIB_INTERNALvoidcrc_fold_init(deflate_state*consts)
 {
 CRC_LOAD(s)
@@ -55,6 +60,7 @@ ZLIB_INTERNAL void crc_fold_init(deflate_state *const s)
 s->strm->adler=0;
 }
 
+__attribute__((target("sse4.2,pclmul")))
 localvoidfold_1(deflate_state*consts,
 __m128i*xmm_crc0, __m128i*xmm_crc1,
 __m128i*xmm_crc2, __m128i*xmm_crc3)
@@ -81,6 +87,7 @@ local void fold_1(deflate_state *const s,
 *xmm_crc3=_mm_castps_si128(ps_res);
 }
 
+__attribute__((target("sse4.2,pclmul")))
 localvoidfold_2(deflate_state*consts,
 __m128i*xmm_crc0, __m128i*xmm_crc1,
 __m128i*xmm_crc2, __m128i*xmm_crc3)
@@ -115,6 +122,7 @@ local void fold_2(deflate_state *const s,
 *xmm_crc3=_mm_castps_si128(ps_res31);
 }
 
+__attribute__((target("sse4.2,pclmul")))
 localvoidfold_3(deflate_state*consts,
 __m128i*xmm_crc0, __m128i*xmm_crc1,
 __m128i*xmm_crc2, __m128i*xmm_crc3)
@@ -155,6 +163,7 @@ local void fold_3(deflate_state *const s,
 *xmm_crc3=_mm_castps_si128(ps_res32);
 }
 
+__attribute__((target("sse4.2,pclmul")))
 localvoidfold_4(deflate_state*consts,
 __m128i*xmm_crc0, __m128i*xmm_crc1,
 __m128i*xmm_crc2, __m128i*xmm_crc3)
@@ -221,6 +230,7 @@ local const unsigned zalign(32) pshufb_shf_table[60] ={
 0x0201008f,0x06050403,0x0a090807,0x0e0d0c0b/* shl 1 (16 -15)/shr15*/
 };
 
+__attribute__((target("sse4.2,pclmul")))
 localvoidpartial_fold(deflate_state*consts, constsize_tlen,
 __m128i*xmm_crc0, __m128i*xmm_crc1,
 __m128i*xmm_crc2, __m128i*xmm_crc3,
@@ -271,6 +281,7 @@ local void partial_fold(deflate_state *const s, const size_t len,
 *xmm_crc3=_mm_castps_si128(ps_res);
 }
 
+__attribute__((target("sse4.2,pclmul")))
 ZLIB_INTERNALvoidcrc_fold_copy(deflate_state*consts,
 unsigned char*dst, constunsigned char*src, longlen)
 {
@@ -427,6 +438,7 @@ local const unsigned zalign(16) crc_mask2[4] ={
 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
 };
 
+__attribute__((target("sse4.2,pclmul")))
 unsigned ZLIB_INTERNALcrc_fold_512to32(deflate_state*consts)
 {
 const__m128ixmm_mask=_mm_load_si128((__m128i*)crc_mask);