package floatmul_pkg; typedef struct packed{logic sign; logic [7:0] exponent; logic [23:0] mantissa} float32_t; endpackage modulefloatmul import floatmul_pkg::*; ( input logic clk, input logic rst, output logic busy, input logic a_valid, input float32_t a_data, output logic a_ready, input logic b_valid, input float32_t b_data, output logic b_ready, output logic o_valid, output float32_t o_data, input logic o_ready ); // Implementation a_ready =/* .. */; b_ready =/* .. */; o_valid =/* .. */; o_data =/* .. */endmodule

modulefloatmul_test_top import floatmul_pkg::*; #( type T_test_case = bit // Test case )( svutest_test_ctrl_if.target tc // Test control from the regress suite ); // DUT control. Injects clock + rst, and collects test-donesvutest_dut_ctrl_ifdc (); // Input and output interfaces to DUTsvutest_req_payload_rsp_if#(float32_t) a (dc.clk, dc.rst); svutest_req_payload_rsp_if#(float32_t) b (dc.clk, dc.rst); svutest_req_payload_rsp_if#(float32_t) o (dc.clk, dc.rst); logic busy; // Instantiate thefloatmulu_fmul ( .clk (dc.clk), .rst (dc.rst), .busy (busy), .a_valid (a.req), .a_data (a.req_payload), .a_ready (a.rsp), .b_valid (b.req), .b_data (b.req_payload), .b_ready (b.rsp), .o_valid (o.req), .o_data (o.req_payload), .o_ready (o.rsp) ); // Set this signal once the test is done always_comb dc.done =~(a.req | b.req | o.req | busy); initialbegin// Instantiate the test case, pass the test_ctrl and dut_ctrl ifs,// along other inputs and outputs. And call run(). T_test_case test = new(tc, dc, a, b, o); test.run(); endendmodule

class floatmul_utest extends svutest_pkg::test_case; valid_data_ready_injector#(float32_t) m_a_injector; // Built-in injector for valid-ready protocol (input a) valid_data_ready_injector#(float32_t) m_b_injector; // Injector for input b valid_data_ready_extractor#(float32_t) m_o_extractor; // Extractor for output cfunction new ( virtual svutest_test_ctrl_if.target vif_test_ctrl, // Test Ctrl virtual svutest_dut_ctrl_if.driver vif_dut_ctrl, // Dut Ctrl virtual svutest_req_payload_rsp_if#(float32_t).driver vif_a, // a virtual svutest_req_payload_rsp_if#(float32_t).driver vif_b, // b virtual svutest_req_payload_rsp_if#(float32_t).target vif_o, // c string test_case_name // Test name ); // Pass test-ctrl, dut_ctrl and test_name to svutest_pkg::test_case::new() super.new(vif_test_ctrl, vif_dut_ctrl, $sformatf("fmul:%0s", test_case_name)); // Create injectors and extractors m_a_injector = new(vif_a); m_b_injector = new(vif_b); m_o_extractor = new(vif_o); // And register them with the test case this.add(m_a_injector); this.add(m_b_injector); this.add(m_o_extractor); endfunction endclass

class floatmul_utest_0_0 extends floatmul_utest; function new ( virtual svutest_test_ctrl_if.target vif_test_ctrl, virtual svutest_dut_ctrl_if.driver vif_dut_ctrl, virtual svutest_req_payload_rsp_if#(float32_t).driver vif_a, virtual svutest_req_payload_rsp_if#(float32_t).driver vif_b, virtual svutest_req_payload_rsp_if#(float32_t).target vif_o ); super.new(vif_test_ctrl, vif_dut_ctrl, vif_a, vif_b, vif_o, "0_0"); endfunction// Override the populate() virtual function to set up the transcations// that will be injected per interface. This is a function that is// run once before actual simulationfunction void populate (); m_a_injector.put('{sign: 1'b0, exponent: '0, mantissa: '0 }); m_b_injector.put('{sign: 1'b0, exponent: '0, mantissa: '0 }); endfunction// Override the check() virtual function to check the number of// outputs emitted and the expectation of each outputfunction void check (); // Get the extractor's internal queue float32_t queue [$] = m_o_extractor.get_queue(); // Check the number of entries emitted from the output `SVUTEST_ASSERT_EQ(queue.size(), 1) // Check the first entry `SVUTEST_ASSERT_EQ(queue[0], '1) endfunction endclass

moduleregress_top; import svutest_pkg::*; import floatmul_utest_pkg::*; // Create the test_ctrl interfacesvutest_test_ctrl_ifi_floatmul_test2_0_0 (); // Instantiate the test_top while passing the test_ctrl interfacefloatmul_test_top#(floatmul_test2_0_0) u_floatmul_test2_0_0 (i_floatmul_test2_0_0); // Another test case, using a macro that does the above in one line `SVUTEST(floatmul_test_top, floatmul_test2_012_012) initialbegin// Create a test-list test_list list = new(); // Add the two test cases to the list by passing the interfaces to add() list.add(i_floatmul_test2_0_0); list.add(i_floatmul_test2_012_012); // Run all tests in the test list list.run(); endendmodule