verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
See what the GitHub community is most excited about today.
Verilator open-source SystemVerilog simulator and lint system
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Common SystemVerilog components
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
HW Design Collateral for Caliptra RoT IP
OpenTitan: Open source silicon root of trust
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
RSD: RISC-V Out-of-Order Superscalar Processor
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Simple single-port AXI memory interface
VeeR EL2 Core
BaseJump STL: A Standard Template Library for SystemVerilog